-- *************************************************************** -- Company: Integrated Device Technology, Inc. -- -- Document number: -- -- Title: BSDL file of Tsi721 (Orion) -- Generated by : Andi Sugandi -- -- Release status: formal issue -- Security level: client use -- BSDL Version 2001 -- Group ownership: DFT Revision Date: -- Released by : -- Revision History: -- Jun 14, 2011: initial release -- -- -- BSDL Syntax Checker -> passed Jun 17, 2011 -- -- -- *************************************************************** -- -- Generated by boundaryScanGenerate v9.0 Wed Jun 30 03:44:05 GMT 2010 on 01/13/11 16:56:37 -- BSDL Version 2001 -- The default acjt_lvl[4:0] which is controlled by IRbits[{17:14},9] is set to 2'h03 -- VHDL package LVS_BSCAN_CELLS is appended at the end of this file. This LVS_BSCAN_CELLS VHDL file needs -- to be uploaded when compiling this BSDL. entity Tsi721 is generic (PHYSICAL_PIN_MAP : string := "FCBGA_143_13"); port ( -- Port List TCK : in bit; TDI : in bit; TMS : in bit; TRSTn : in bit; TDO : out bit; PCTP : out bit_vector( 3 downto 0 ); PCTN : out bit_vector( 3 downto 0 ); PCRP : in bit_vector( 3 downto 0 ); PCRN : in bit_vector( 3 downto 0 ); PCRSTOn : inout bit; TEST_BCE : in bit; TEST_ON : linkage bit; TEST_BIDIR_CTL : in bit; RSTn : linkage bit; SRRSTOn : inout bit; SRTP : out bit_vector( 3 downto 0 ); SRTN : out bit_vector( 3 downto 0 ); SRRP : in bit_vector( 3 downto 0 ); SRRN : in bit_vector( 3 downto 0 ); I2C_SDA : inout bit; MECS : inout bit; SR_BOOT : in bit; I2C_SCL : inout bit; CLKMOD : in bit; GPIO : inout bit_vector( 15 downto 0 ); STRAP_RATE : in bit_vector( 2 downto 0 ); PCCLKP : linkage bit; PCCLKN : linkage bit; REFCLKP : linkage bit; REFCLKN : linkage bit; PCBIAS : linkage bit; SRBIAS : linkage bit; VDD : linkage bit_vector( 7 downto 0 ); AVDD25 : linkage bit_vector( 7 downto 0 ); AVDD10 : linkage bit_vector( 7 downto 0 ); VDDIO : linkage bit_vector( 9 downto 0 ); AVTT : linkage bit_vector( 7 downto 0 ); VSS : linkage bit_vector( 27 downto 0 ) ); use STD_1149_1_2001.all; use STD_1149_6_2003.all; use LVS_BSCAN_CELLS.all; attribute COMPONENT_CONFORMANCE of Tsi721: entity is "STD_1149_1_2001"; --Pin mappings attribute PIN_MAP of Tsi721: entity is PHYSICAL_PIN_MAP; constant FCBGA_143_13: PIN_MAP_STRING := "TCK : E11 , " & "TDI : F11 , " & "TMS : H11 , " & "TRSTn : J11 , " & "TDO : D11 , " & "PCTP :(A10 , " & -- PCTP[3] "A9 , " & -- PCTP[2] "A6 , " & -- PCTP[1] "A5 ), " & -- PCTP[0] "PCTN :(B10 , " & -- PCTN[3] "B9 , " & -- PCTN[2] "B6 , " & -- PCTN[1] "B5 ), " & -- PCTN[0] "PCRP :(A11 , " & -- PCRP[3] "A8 , " & -- PCRP[2] "A7 , " & -- PCRP[1] "A4 ), " & -- PCRP[0] "PCRN :(B11 , " & -- PCRN[3] "B8 , " & -- PCRN[2] "B7 , " & -- PCRN[1] "B4 ), " & -- PCRN[0] "PCRSTOn : D12 , " & "TEST_BCE : E12 , " & "TEST_ON : F12 , " & "TEST_BIDIR_CTL : G12 , " & "RSTn : H12 , " & "SRRSTOn : J12 , " & "SRTP :(M10 , " & -- SRTP[3] "M9 , " & -- SRTP[2] "M6 , " & -- SRTP[1] "M5 ), " & -- SRTP[0] "SRTN :(L10 , " & -- SRTN[3] "L9 , " & -- SRTN[2] "L6 , " & -- SRTN[1] "L5 ), " & -- SRTN[0] "SRRP :(M11 , " & -- SRRP[3] "M8 , " & -- SRRP[2] "M7 , " & -- SRRP[1] "M4 ), " & -- SRRP[0] "SRRN :(L11 , " & -- SRRN[3] "L8 , " & -- SRRN[2] "L7 , " & -- SRRN[1] "L4 ), " & -- SRRN[0] "I2C_SDA : M1 , " & "MECS : M2 , " & "SR_BOOT : M3 , " & "I2C_SCL : L1 , " & "CLKMOD : L2 , " & "GPIO :(G2 , " & -- GPIO[15] "F2 , " & -- GPIO[14] "E2 , " & -- GPIO[13] "D2 , " & -- GPIO[12] "C2 , " & -- GPIO[11] "B2 , " & -- GPIO[10] "A2 , " & -- GPIO[9] "K1 , " & -- GPIO[8] "J1 , " & -- GPIO[7] "H1 , " & -- GPIO[6] "G1 , " & -- GPIO[5] "F1 , " & -- GPIO[4] "E1 , " & -- GPIO[3] "D1 , " & -- GPIO[2] "C1 , " & -- GPIO[1] "B1 ), " & -- GPIO[0] "STRAP_RATE :(K2 , " & -- STRAP_RATE[2] "J2 , " & -- STRAP_RATE[1] "H2 ), " & -- STRAP_RATE[0] "PCCLKP : A12 , " & "PCCLKN : B12 , " & "REFCLKP : M12 , " & "REFCLKN : L12 , " & "PCBIAS : C12 , " & "SRBIAS : K12 , " & "VDD :(H8 , " & -- VDD[7] "H5 , " & -- VDD[6] "G7 , " & -- VDD[5] "G6 , " & -- VDD[4] "F7 , " & -- VDD[3] "F6 , " & -- VDD[2] "E8 , " & -- VDD[1] "E5 ), " & -- VDD[0] "AVDD25 :(K8 , " & -- AVDD25[7] "K7 , " & -- AVDD25[6] "K6 , " & -- AVDD25[5] "K5 , " & -- AVDD25[4] "C8 , " & -- AVDD25[3] "C7 , " & -- AVDD25[2] "C6 , " & -- AVDD25[1] "C5 ), " & -- AVDD25[0] "AVDD10 :(J9 , " & -- AVDD10[7] "J8 , " & -- AVDD10[6] "H9 , " & -- AVDD10[5] "G9 , " & -- AVDD10[4] "F9 , " & -- AVDD10[3] "E9 , " & -- AVDD10[2] "D9 , " & -- AVDD10[1] "D8 ), " & -- AVDD10[0] "VDDIO :(H10 , " & -- VDDIO[9] "J3 , " & -- VDDIO[8] "D3 , " & -- VDDIO[7] "H3 , " & -- VDDIO[6] "G10 , " & -- VDDIO[5] "G3 , " & -- VDDIO[4] "F10 , " & -- VDDIO[3] "F3 , " & -- VDDIO[2] "E10 , " & -- VDDIO[1] "E3 ), " & -- VDDIO[0] "AVTT :(J5 , " & -- AVTT[7] "J4 , " & -- AVTT[6] "H4 , " & -- AVTT[5] "G4 , " & -- AVTT[4] "F4 , " & -- AVTT[3] "E4 , " & -- AVTT[2] "D5 , " & -- AVTT[1] "D4 ), " & -- AVTT[0] "VSS :(L3 , " & -- VSS[27] "A3 , " & -- VSS[26] "C11 , " & -- VSS[25] "G11 , " & -- VSS[24] "K11 , " & -- VSS[23] "K10 , " & -- VSS[22] "K9 , " & -- VSS[21] "K4 , " & -- VSS[20] "K3 , " & -- VSS[19] "J10 , " & -- VSS[18] "J7 , " & -- VSS[17] "J6 , " & -- VSS[16] "H7 , " & -- VSS[15] "H6 , " & -- VSS[14] "G8 , " & -- VSS[13] "G5 , " & -- VSS[12] "F8 , " & -- VSS[11] "F5 , " & -- VSS[10] "E7 , " & -- VSS[9] "E6 , " & -- VSS[8] "D10 , " & -- VSS[7] "D7 , " & -- VSS[6] "D6 , " & -- VSS[5] "C10 , " & -- VSS[4] "C9 , " & -- VSS[3] "C4 , " & -- VSS[2] "C3 , " & -- VSS[1] "B3 ) " ; -- VSS[0] attribute PORT_GROUPING of Tsi721 : entity is "Differential_Current ( (PCTP(0), PCTN(0)), " & "(PCRP(0), PCRN(0)), " & "(PCTP(1), PCTN(1)), " & "(PCRP(1), PCRN(1)), " & "(PCTP(2), PCTN(2)), " & "(PCRP(2), PCRN(2)), " & "(PCTP(3), PCTN(3)), " & "(PCRP(3), PCRN(3)), " & "(SRTP(0), SRTN(0)), " & "(SRRP(0), SRRN(0)), " & "(SRTP(1), SRTN(1)), " & "(SRRP(1), SRRN(1)), " & "(SRTP(2), SRTN(2)), " & "(SRRP(2), SRRN(2)), " & "(SRTP(3), SRTN(3)), " & "(SRRP(3), SRRN(3))) " ; attribute TAP_SCAN_RESET of TRSTn : signal is true; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; attribute TAP_SCAN_OUT of TDO : signal is true; attribute TAP_SCAN_CLOCK of TCK : signal is (1.0000000000000000000e+07, BOTH); attribute COMPLIANCE_PATTERNS of Tsi721 : entity is "(TEST_BCE,TEST_BIDIR_CTL) (11)"; attribute INSTRUCTION_LENGTH of Tsi721: entity is 62; attribute INSTRUCTION_OPCODE of Tsi721: entity is "IDCODE (11111111111111111111111111111111111111111111111111111111111110)," & "BYPASS (00000000000000000000000000000000000000000000000000000000000000, 11111111111111111111111111111111111111111111111111111111111111)," & "EXTEST (11111111111111111111111111110111101111111111111111111111101000)," & "EXTEST_PULSE (11111111111111111111111111110111101111111111101111111111101000)," & "EXTEST_TRAIN (11111111111111111111111111110111101111111111011111111111101000)," & "SAMPLE (11111111111111111111111111110111101111111111111111111111111000)," & "PRELOAD (11111111111111111111111111110111101111111111111111111111111000)," & "HIGHZ (11111111111111111111111111110111101111111111111111111111001111)," & "CLAMP (11111111111111111111111111111111111111111111111111111111101111) " ; attribute INSTRUCTION_CAPTURE of Tsi721: entity is "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01"; attribute IDCODE_REGISTER of Tsi721: entity is "0000" & -- version "1000000010101011" & -- part number "00000110011" & -- manufacturer's identity "1"; -- required by 1149.1 attribute REGISTER_ACCESS of Tsi721: entity is "BOUNDARY ( EXTEST_PULSE, EXTEST_TRAIN )," & "BOUNDARY ( SAMPLE, PRELOAD )," & "BYPASS ( HIGHZ, CLAMP, BYPASS ) " ; --Boundary scan definition attribute BOUNDARY_LENGTH of Tsi721: entity is 83; attribute BOUNDARY_REGISTER of Tsi721: entity is -- num cell port function safe [ccell disval rslt] " 82 (BC_1 , * , control , 0 ) ,"& " 81 (AC_1 , PCTP(0) , output3 , X , 82 , 0 , Z ),"& " 80 (BC_4 , PCRP(0) , observe_only , X ) ,"& " 79 (BC_4 , PCRN(0) , observe_only , X ) ,"& " 78 (BC_1 , * , control , 0 ) ,"& " 77 (AC_1 , PCTP(1) , output3 , X , 78 , 0 , Z ),"& " 76 (BC_4 , PCRP(1) , observe_only , X ) ,"& " 75 (BC_4 , PCRN(1) , observe_only , X ) ,"& " 74 (BC_1 , * , control , 0 ) ,"& " 73 (AC_1 , PCTP(2) , output3 , X , 74 , 0 , Z ),"& " 72 (BC_4 , PCRP(2) , observe_only , X ) ,"& " 71 (BC_4 , PCRN(2) , observe_only , X ) ,"& " 70 (BC_1 , * , control , 0 ) ,"& " 69 (AC_1 , PCTP(3) , output3 , X , 70 , 0 , Z ),"& " 68 (BC_4 , PCRP(3) , observe_only , X ) ,"& " 67 (BC_4 , PCRN(3) , observe_only , X ) ,"& " 66 (BC_0 , * , internal , 0 ) ,"& " 65 (BC_0 , * , internal , 0 ),"& " 64 (BC_2 , * , control , 1 ) ,"& " 63 (LV_BC_7 , PCRSTOn , bidir , X , 64 , 1 , Z ),"& " 62 (BC_2 , * , control , 1 ) ,"& " 61 (LV_BC_7 , SRRSTOn , bidir , X , 62 , 1 , Z ),"& " 60 (BC_1 , * , control , 0 ) ,"& " 59 (AC_1 , SRTP(0) , output3 , X , 60 , 0 , Z ),"& " 58 (BC_4 , SRRP(0) , observe_only , X ) ,"& " 57 (BC_4 , SRRN(0) , observe_only , X ) ,"& " 56 (BC_1 , * , control , 0 ) ,"& " 55 (AC_1 , SRTP(1) , output3 , X , 56 , 0 , Z ),"& " 54 (BC_4 , SRRP(1) , observe_only , X ) ,"& " 53 (BC_4 , SRRN(1) , observe_only , X ) ,"& " 52 (BC_1 , * , control , 0 ) ,"& " 51 (AC_1 , SRTP(2) , output3 , X , 52 , 0 , Z ),"& " 50 (BC_4 , SRRP(2) , observe_only , X ) ,"& " 49 (BC_4 , SRRN(2) , observe_only , X ) ,"& " 48 (BC_1 , * , control , 0 ) ,"& " 47 (AC_1 , SRTP(3) , output3 , X , 48 , 0 , Z ),"& " 46 (BC_4 , SRRP(3) , observe_only , X ) ,"& " 45 (BC_4 , SRRN(3) , observe_only , X ) ,"& " 44 (BC_2 , * , control , 1 ) ,"& " 43 (LV_BC_7 , I2C_SDA , bidir , X , 44 , 1 , Z ),"& " 42 (BC_2 , * , control , 1 ) ,"& " 41 (LV_BC_7 , MECS , bidir , X , 42 , 1 , Z ),"& " 40 (BC_2 , SR_BOOT , input , X ) ,"& " 39 (BC_2 , * , control , 1 ) ,"& " 38 (LV_BC_7 , I2C_SCL , bidir , X , 39 , 1 , Z ),"& " 37 (BC_2 , CLKMOD , input , X ) ,"& " 36 (BC_2 , * , control , 1 ) ,"& " 35 (LV_BC_7 , GPIO(8) , bidir , X , 36 , 1 , Z ),"& " 34 (BC_2 , STRAP_RATE(2) , input , X ) ,"& " 33 (BC_2 , * , control , 1 ) ,"& " 32 (LV_BC_7 , GPIO(7) , bidir , X , 33 , 1 , Z ),"& " 31 (BC_2 , STRAP_RATE(1) , input , X ) ,"& " 30 (BC_2 , * , control , 1 ) ,"& " 29 (LV_BC_7 , GPIO(6) , bidir , X , 30 , 1 , Z ),"& " 28 (BC_2 , STRAP_RATE(0) , input , X ) ,"& " 27 (BC_2 , * , control , 1 ) ,"& " 26 (LV_BC_7 , GPIO(5) , bidir , X , 27 , 1 , Z ),"& " 25 (BC_2 , * , control , 1 ) ,"& " 24 (LV_BC_7 , GPIO(15) , bidir , X , 25 , 1 , Z ),"& " 23 (BC_2 , * , control , 1 ) ,"& " 22 (LV_BC_7 , GPIO(4) , bidir , X , 23 , 1 , Z ),"& " 21 (BC_2 , * , control , 1 ) ,"& " 20 (LV_BC_7 , GPIO(14) , bidir , X , 21 , 1 , Z ),"& " 19 (BC_2 , * , control , 1 ) ,"& " 18 (LV_BC_7 , GPIO(3) , bidir , X , 19 , 1 , Z ),"& " 17 (BC_2 , * , control , 1 ) ,"& " 16 (LV_BC_7 , GPIO(13) , bidir , X , 17 , 1 , Z ),"& " 15 (BC_2 , * , control , 1 ) ,"& " 14 (LV_BC_7 , GPIO(2) , bidir , X , 15 , 1 , Z ),"& " 13 (BC_2 , * , control , 1 ) ,"& " 12 (LV_BC_7 , GPIO(12) , bidir , X , 13 , 1 , Z ),"& " 11 (BC_2 , * , control , 1 ) ,"& " 10 (LV_BC_7 , GPIO(1) , bidir , X , 11 , 1 , Z ),"& " 9 (BC_2 , * , control , 1 ) ,"& " 8 (LV_BC_7 , GPIO(11) , bidir , X , 9 , 1 , Z ),"& " 7 (BC_2 , * , control , 1 ) ,"& " 6 (LV_BC_7 , GPIO(0) , bidir , X , 7 , 1 , Z ),"& " 5 (BC_2 , * , control , 1 ) ,"& " 4 (LV_BC_7 , GPIO(10) , bidir , X , 5 , 1 , Z ),"& " 3 (BC_2 , * , control , 1 ) ,"& " 2 (LV_BC_7 , GPIO(9) , bidir , X , 3 , 1 , Z ),"& " 1 (BC_0 , * , internal , 0 ) ,"& " 0 (BC_0 , * , internal , 0 ) "; attribute AIO_COMPONENT_CONFORMANCE of Tsi721: entity is "STD_1149_6_2003"; attribute AIO_Pin_Behavior of Tsi721: entity is "PCTP(0) ;"& "PCRP(0)[80] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "PCTP(1) ;"& "PCRP(1)[76] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "PCTP(2) ;"& "PCRP(2)[72] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "PCTP(3) ;"& "PCRP(3)[68] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "SRTP(0) ;"& "SRRP(0)[58] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "SRTP(1) ;"& "SRRP(1)[54] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "SRTP(2) ;"& "SRRP(2)[50] : LP_Time=2.30e-07 HP_Time=7.00e-06;"& "SRTP(3) ;"& "SRRP(3)[46] : LP_Time=2.30e-07 HP_Time=7.00e-06"; end Tsi721; -- VHDL package to be uploaded -- --package LVS_BSCAN_CELLS is -- use STD_1149_1_2001.all; -- constant LV_BC_7: CELL_INFO; -- --end LVS_BSCAN_CELLS; --package body LVS_BSCAN_CELLS is -- use STD_1149_1_2001.all; -- constant LV_BC_7: CELL_INFO := -- ((BIDIR_IN, EXTEST, PI), (BIDIR_OUT, EXTEST, PO), -- (BIDIR_IN, SAMPLE, PI), (BIDIR_OUT, SAMPLE, PI), -- (BIDIR_IN, INTEST, X), (BIDIR_OUT, INTEST, PI)); -- --end LVS_BSCAN_CELLS; --